The Design and Implementation of a Multi-queue Buffer for Vlsi Communication Switches †

Small n ×n switches are key components of multistage interconnection networks and communication coprocessors used in multiprocessors and multicomputers. Communication latency and throughput are critically dependent on the structure of the internal buffers in these switches. We have previously introduced the architecture of a new type of buffer, called a dynamically-allocated multi-queue (DAMQ) buffer, that provides non-FIFO message handling and can support higher throughput at lower latency than the commonly used FIFO buffer. In this paper, we present a micro-architecture and VLSI implementation of a DAMQ buffer. We discuss design tradeoffs for the DAMQ buffer’s datapath and present a floorplan and the timing of the major functional units. This paper shows that in VLSI switches, with buffers that can store multiple packets, additional chip area is better used for the control of DAMQ buffers than for increased buffer space in simpler FIFO buffers.